description designed for pulse width modulated (pwm) current control of bipolar stepper motors, the A3964 is capable of continuous output currents to 800 ma and operating voltages to 30 v. internal fixed off-time pwm current-control circuitry can be used to regulate the maximum load current to a desired value. an internal precision voltage reference is provided to improve motor peak-current control accuracy. the peak load current limit is set by the user?s selection of an external resistor divider and current-sensing resistors. the fixed off-time pulse duration is set by user-selected external rc timing networks. the capacitor in the rc timing network also determines a user-selectable blanking window that prevents false triggering of the pwm current control circuitry during switching transitions. this eliminates the need for two external rc filter networks on the current-sensing comparator inputs. for each bridge the phase input controls load current polarity by selecting the appropriate source and sink driver pair. for 29319.28g features and benefits ? 800 ma continuous output current rating ? 30 v output voltage rating ? internal pwm current control, saturated sink drivers ? internally generated, precision 2.5 v reference ? internal transient-suppression diodes ? internal thermal-shutdown circuitry ? crossover-current protection, uvlo protection dual full-bridge pwm motor driver continued on the next page? package: 20 pin soic (suffix lb) functional block diagram not to scale A3964 2.5 v reference 14 5 2 r s 19 r s v ref(in) v cc out 1a out 1b out 2a out 2b sense 1 sense 2 logic supply load supply enable 1 enable 2 rc 1 rc 2 phase 1 phase 2 v bb 1 C + one shot source disable C + source disable 2 one shot pwm 1 pwm 2 uvlo & tsd 8 10 9 31 4 1820 7 12 11 13 17 r t r t c t c t dw g . fp-033-1 ref out ref in 61516 r a r b
dual full-bridge pwm motor driver A3964 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com each bridge the enable input, when held high, disables the output drivers. special power-up sequencing is not required. internal circuit protection includes thermal shutdown with hysteresis, transient- suppression diodes, and crossover-current protection. the A3964 is supplied in a 20-lead soic with internally fused pins for enhanced thermal dissipation. the package is lead (pb) free with 100% matte tin leadframe plating. the power pins are at ground potential and need no electrical isolation. 1 v bb 2 1 2 3 4 5 6 7 9 20 19 18 17 16 15 14 13 12 11 10 9 8 2 1 v cc pwm 1 pwm 2 ground ground ground ground phase 2 v ref(out) 2 rc 1 rc v ref(in) phase 1 2b out sense 2 2a out 1a out sense 1 1b out load supply logic supply enable 1 enable 2 selection guide part number packing package A3964slb-t 20-pin soic with internally fused pins 37 per tube A3964slbtr-t 20-pin soic with internally fused pins 1000 per reel description (continued) absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 33 v logic supply voltage v cc 7.0 v input voltage v in ?0.3 to v dd + 0.3 v sense voltage v s 1.0 v reference output current i ref(out) 1.0 ma output current i out output current rating may be limited by duty cycle, am- bient temperature, and heat sinking. under any set of conditions, do not exceed the speci ed current rating or a junction temperature of 150 c. t w = 10 s 1.0 a continuous 800 ma package power dissipation p d see graph ?? operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) fault conditions that produce excessive junction temperature will activate the device?s thermal shutdown circuitry. these conditions can be toler- ated but should be avoided. 150 oc storage temperature t stg ?55 to 150 oc 50 75 100 125 150 5 1 0 allowable package power dissipation (w) temperature in o c 4 3 2 25 r = 6.0 o c/w q jt suffix 'lb', r = 61 o c/w q ja pin-out diagram
dual full-bridge pwm motor driver A3964 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com truth table enable phase out a out b h x off off l h h l l l l h electrical characteristics at t a = +25c, v bb = 30 v, v cc = 4.75 v to 5.25 v, v s = 0 v, 30 k and 1000 pf rc to ground (unless noted otherwise) limits characteristic symbol test conditions min. typ. max. units load supply voltage range v bb operating, i out = 800 ma, l = 3 mh 5.0 ? 30 v output sustaining voltage v ce(sus) i out = 800 ma, l = 3 mh, v bb = 33 v 33 ? ? v output leakage current i cex v out = v bb = 33 v ? <1.0 50 a v out = 0 v, v bb = 33 v ? <1.0 -50 a output saturation voltage v ce(sat) source driver, i out = -500 ma ? 1.0 1.2 v source driver, i out = -750 ma ? 1.1 1.5 v source driver, i out = -800 ma ? ? 1.7 v sink driver, i out = +500 ma ? 0.3 0.6 v sink driver, i out = +750 ma ? 0.5 1.2 v sink driver, i out = +800 ma ? ? 1.5 v clamp diode forward voltage v f i f = 500 ma ? 1.1 1.4 v (sink or source) i f = 750 ma ? 1.3 1.6 v i f = 800 ma ? ? 1.7 v motor supply current i bb(on) v enable = 0.8 v ? 2.0 4.0 ma (no load) i bb(off) v enable = 2.4 v ? 0 500 a output drivers x = irrelevant continued on the next page ?
dual full-bridge pwm motor driver A3964 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com logic supply voltage range v cc operating 4.75 ? 5.25 v logic input voltage v in(1) 2.4 ? ? v v in(0) ? ? 0.8 v logic input current i in(1) v in = 2.4 v ? <1.0 20 a i in(0) v in = 0.8 v ? <-2.0 -200 a reference output voltage v ref(out) v cc = 5.0 v, i ref(out) = 90 to 900 a 2.45 2.50 2.55 v reference output current i ref(out) 3 k r d = r a + r b 15 k 150 ? 900 a ref. input offset current i os v ref(in) = 1 v -2.5 0 1.0 a comparator input offset volt. v io v ref(in) = 0 v -6.0 0 6.0 mv comparator input volt. range v ref operating -0.3 ? 1.0 v pwm rc fixed off-time t off rc c t = 1000 pf, r t = 30 k 27 30 33 s pwm propagation delay time t pwm comparator trip to source off ? 1.2 2.0 s pwm minimum on time t on(min) c t = 1000 pf, r t 15 k , v cc = 5 v ? 2.5 3.6 s propagation delay times t pd i out = 800 ma, 50% to 90%: enable on to source on ? 3.2 ? s enable off to source off ? 1.2 ? s enable on to sink on ? 3.2 ? s enable off to sink off ? 0.7 ? s phase change to sink on ? 3.2 ? s phase change to source on ? 3.2 ? s phase change to sink off ? 0.7 ? s phase change to source off ? 1.2 ? s thermal shutdown temp. t j ? 165 ? c thermal shutdown hysteresis ? t j ? 15 ? c uvlo disable threshold decreasing v cc 4.20 4.40 4.65 v uvlo hysteresis uvlo enable volt. - uvlo disable volt. 0.075 0.125 0.175 v uvlo enable threshold increasing v cc 4.375 4.525 4.725 v logic supply current i cc(on) v enable 1 = v enable 2 = 0.8 v ? 60 85 ma i cc(off) v enable 1 = v enable 2 = 2.4 v ? 13 17 ma logic supply current ? i cc(on) v enable 1 = v enable 2 = 0.8 v ? 0.18 ? ma/c temperature coef cient limits characteristic symbol test conditions min. typ. max. units electrical characteristics (continued) at t a = +25c, v bb = 30 v, v cc = 4.75 v to 5.25 v, v sense = 0 v, 30 k and 1000 pf rc to ground (unless noted otherwise) notes: 1. typical data is for design information only. 2. negative current is de ned as coming out of (sourcing) the speci ed device terminal. control logic
dual full-bridge pwm motor driver A3964 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com internal pwm current control. the A3964 contain a xed off-time, pulse width modulated (pwm) current-control circuit that can be used to limit the load current to a desired value. the peak value of the current limiting (i trip ) is set by the selection of an external current-sensing resistor (r s ) and reference input voltage (v ref(in) ). the internal circuitry compares the voltage across the external sense resistor to the voltage on the reference input terminal (v ref(in) ) resulting in a transconductance function approximated by: i trip v ref(in) r s the reference input voltage is typically set with a resistor divider from v ref(out) . to ensure proper operation of the voltage reference, the resistor divider should have an impedance of 3 k to 15 k (r d = r a +r b ). within this range, a low impedance will minimize the effect of the ref in input offset current. the current-control circuitry limits the load current as follows: when the load current reaches i trip , the comparator resets a latch that turns off the selected source driver. the load inductance causes the current to recirculate through the sink driver and yback diode. for each bridge, the user selects an external resistor (r t ) and capacitor (c t ) to determine the time period (t off = r t c t ) during which the source driver remains disabled (see the rc fixed off-time section, below). the range of recommended values for c t and r t are 1000 pf to 1500 pf and 15 k to 100 k respectively. for optimal load current regulation, c t is normally set to 1000 pf (see the load current regulation section, below). at the end of the rc interval, the source driver is enabled allowing the load current to increase again. the pwm cycle repeats, maintaining the peak load current at the desired value. rc blanking. in addition to determining the xed off-time of the pwm control circuit, the c t component sets the comparator blanking time. this function blanks the output of the comparator when the outputs are switched by the internal current-control circuitry (or by the phase or enable inputs). the comparator output is blanked to prevent false over-current detections due to reverse-recovery currents of the clamp diodes, and/or switching transients related to distributed capacitance in the load. during internal pwm operation, at the end of the t off time, the comparator?s output is blanked and c t begins to be charged from approximately 1.1 volts by an internal current source of approximately 1 ma. the comparator output remains blanked until the voltage on c t reaches approximately 3 volts. when a transition of the phase input occurs, c t is discharged to near ground during the crossover delay time (the crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). after the crossover delay, c t is charged by an internal current source of approximately 1 ma. the comparator output remains blanked until the voltage on c t reaches approximately 3 volts. when the device is disabled, via the enable input, c t is discharged to near ground. when the device is re-enabled, c t is charged by an internal current source of approximately 1 ma. the comparator output remains blanked until the voltage on c t reaches approximately 3 volts. the minimum recommended value for c t is 1000 pf. this value ensures that the blanking time is suf cient to avoid false trips of the comparator under normal operating conditions. for optimal regulation of the load current, the above value for c t is recommended and the value of r t can be sized to determine t off . for more information regarding load current regulation, see below. load current regulation. because the device operates in a slow current-decay mode (2-quadrant pwm mode), there is a limit to the lowest level that the pwm current control circuitry can regulate load current. the limitation is due to the minimum pwm duty cycle, which is a function of the user-selected value of t off and the minimum on-time pulse t on(min) max that occurs each time the pwm latch is reset. if the motor is not rotating, as in the case of a stepper motor in hold/detent mode, a brush dc motor when stalled or at startup, the worst case value of current regulation can be approximated by: [(v bb ? v sat(source+sink) ) x t on(min) max] ? [1.05 (v sat(sink) + v f ) x t off ] 1.05 (t on(min) max + t off ) x r load i av g where t off = r t c t , r load is the series resistance of the load, v bb is the motor supply voltage and t on(min) max is speci ed in the electrical characteristics table. when the motor is rotating, the back emf generated will in uence the above relationship. for brush dc motor applications, the current regulation is improved. for stepper motor applications when the motor is rotating, the effect is dependent on the polarity and magnitude of the motor?s back emf. functional description
dual full-bridge pwm motor driver A3964 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the following procedure can be used to evaluate the worst case internal pwm load current regulation in the system: set v ref(in) to 0 volts. with the load connected and the pwm current control operating in slow decay mode, use an oscilloscope to measure the time the output is low (sink on) for the output that is chopping. this is the typical minimum on time (t on(min) typ) for the device. the c t then should be increased until the measured value of t on(min) is equal to t on(min) max as speci ed in the electrical characteristics table. when the new value of c t has been set, the value of r t should be decreased so the value for t off = r t c t (with the arti cially increased value of c t ) is equal to the nominal design value. the worst-case load-current regulation then can be measured in the system under operating conditions. pwm of the phase and enable inputs. the phase and enable inputs can be pulse width modulated to regulate load current. typical propagation delays from the phase and enable inputs to transitions of the power outputs are speci ed in the electrical characteristics table. if the internal pwm current control is used, the comparator blanking function is active during phase and enable transitions. this eliminates false tripping of the over-current comparator caused by switching transients (see the rc blanking section, above). enable pwm. toggling the enable input turns on and off the selected source and sink drivers. the corresponding pair of yback and ground clamp diodes conduct after the drivers are disabled, resulting in fast current decay. when the device is enabled the internal current control circuitry will be active and can be used to limit the load current in a slow current-decay mode. phase pwm. toggling the phase terminal selects which sink/ source pair is enabled, producing a load current that varies with the duty cycle and remains continuous at all times. this can have added bene ts in bidirectional brush dc servo motor applications as the transfer function between the duty cycle on the phase input and the average voltage applied to the motor is more linear than in the case of enable pwm control (which produces a discontinuous current at low current levels). miscellaneous information. an internally generated dead time prevents crossover currents that can occur when switching phase. thermal protection circuitry turns off all drivers should the junction temperature reach +165c (typical). this is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. the hysteresis of the thermal shutdown circuit is approximately 15c. application notes current sensing. the actual peak load current (i peak ) will be above the calculated value of i trip due to delays in the turn off of the drivers. the amount of overshoot can be approximated by: (v bb ? [(i trip x r load ) + v bemf ]) x t pwm l load i os where v bb is the motor supply voltage, v bemf is the back-emf voltage of the load, r load and l load are the resistance and inductance of the load respectively, and t pwm is speci ed in the electrical characteristics table. to minimize current sensing inaccuracies caused by ground trace ir drops, each current-sensing resistor should have a separate return to the ground terminal of the device. for low-value sense resistors, the ir drops in the pcb can be signi cant and should be taken into account. the use of sockets should be avoided as their contact resistance can cause variations in the effective value of r s . generally, larger values of r s reduce the aforementioned effects but can result in excessive heating and power loss in the sense resistor. the selected value of r s should not cause the absolute maximum voltage rating of 1.0 v, for the sense terminal, to be exceeded. the recommended value of r s is in the range of: 0.5 i trip max r s 50% if desired, the reference input voltage can be ltered by placing a capacitor from ref in to ground. the ground return for this capacitor as well as r b should be independent from the high- current power-ground trace to avoid changes in ref in due to ir drops. thermal considerations. for reliable operation, it is recommended that the maximum junction temperature be kept below 110c to 125c. the junction temperature can be measured best by attaching a thermocouple to the power tab/ batwing of the device and measuring the tab temperature, t tab . the junction temperature can then be approximated by using the formula: t j t tab + (2 i load v f r jt ) where v f can be chosen from the electrical speci cation table for the given level of i load . the value for r jt is approximately 6c/w. the power dissipation of the batwing packages can be improved by 20 to 30% by adding a section of printed circuit board copper (typically 6 to 18 square centimeters) connected to the batwing terminals of the device.
dual full-bridge pwm motor driver A3964 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the thermal performance in applications that run at high load currents and/or high duty cycles can be improved by adding external diodes from each output to ground in parallel with the internal diodes. fast-recovery ( 200 ns) diodes should be used to minimize switching losses. the load supply terminal, v bb , should be decoupled with an electrolytic capacitor ( 47 f is recommended) placed as close to the device as is physically practical. to minimize the effect of system ground ir drops on the logic and reference input signals the system ground should have a low-resistance return to the load supply voltage. see also the current sensing and thermal considerations sections, above. fixed off-time selection. with increasing values of t off , switching losses will decrease, low-level load current regulation will improve, emi will be reduced, the pwm frequency will decrease, and ripple current will increase. the value of t off can be chosen for optimization of these parameters. for applications where audible noise is a concern, typical values of t off are chosen to be in the range of 15 to 35 s. 2 1 20 2 1 20 a 2.65 max c seating plane c 0.10 20x a terminal #1 mark area gauge plane seating plane b 2.25 0.65 9.50 1.27 pcb layout reference view all dimensions nominal, not for tooling use dimensions in millimeters pins 5, 6, 15 and 16 internally fused (reference jedec ms-013 ac) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b reference pad layout (reference ipc soic127p1030x265-20m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances 1.27 0.25 0.20 0.10 0.41 0.10 12.800.20 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 lb package 20-pin soicw copyright ?1997-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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